1. Field of the Invention
The present disclosure generally relates to the formation of integrated circuits, and, more particularly, to a process flow for forming a passivation layer for receiving bumps connecting the integrated circuit to a package substrate, wherein the passivation layer may comprise silicon dioxide and silicon oxynitride (SiON).
2. Description of the Related Art
In manufacturing integrated circuits, it is usually necessary to package a chip and provide leads and terminals for connecting the chip circuitry with the periphery. In some packaging techniques, chips, chip packages or other appropriate units may be connected by means of solder balls, formed from so-called solder bumps, that are formed on a corresponding layer, which will be referred to herein as a passivation layer, of at least one of the units, for instance on a dielectric layer of the microelectronic chip. In order to connect the microelectronic chip with the corresponding carrier, the surfaces of two respective units to be connected, i.e., the microelectronic chip comprising, for instance, a plurality of integrated circuits and a corresponding package, have formed thereon adequate pad arrangements to electrically connect the two units after reflowing the solder bumps provided on at least one of the units, for instance on the microelectronic chip. In other techniques, solder bumps may have to be formed that are to be connected to corresponding wires, or the solder bumps may be brought into contact with corresponding pad areas of another substrate acting as a heat sink. Consequently, it may be necessary to form a large number of solder bumps that may be distributed over the entire chip area, thereby providing, for example, the I/O capability as well as the desired low-capacitance arrangement required for high frequency applications of modern microelectronic chips that usually include complex circuitry, such as microprocessors, storage circuits and the like, and/or include a plurality of integrated circuits forming a complete complex circuit system.
In modern integrated circuits, highly conductive metals, such as copper and alloys thereof, are used to accommodate the high current densities encountered during the operation of the devices. Consequently, the metallization layers may comprise metal lines and vias formed from copper or copper alloys, wherein the last metallization layer may provide contact areas for connecting to the solder bumps to be formed above the copper-based contact areas. The processing of copper in the subsequent process flow for forming the solder bumps, which is itself a highly complex manufacturing phase, may be performed on the basis of the well-established metal aluminum that has been effectively used for forming solder bump structures in complex aluminum-based microprocessors. For this purpose, the dielectric material of the passivation layer may be deposited and may be patterned prior to or after the deposition of an appropriate barrier and adhesion layer. In some well-established regimes for forming the passivation layer, silicon dioxide followed by silicon oxynitride (SiON) are formed which may be patterned to receive a barrier layer, such as tantalum, and an aluminum layer, which may then also be patterned to provide contact pads at desired locations for forming thereon the solder bumps.
In order to provide hundreds or thousands of mechanically well-fastened solder bumps on corresponding pads, the attachment procedure of the solder bumps requires a careful design, since the entire device may be rendered useless upon failure of only one of the solder bumps. For this reason, one or more carefully chosen layers are generally placed between the solder bumps and the underlying substrate or wafer including the aluminum-covered contact areas. In addition to the important role these interfacial layers, herein also referred to as underbump metallization layers, may play in endowing a sufficient mechanical adhesion of the solder bump to the underlying contact area and the surrounding passivation material, the underbump metallization has to meet further requirements with respect to diffusion characteristics and current conductivity. Regarding the former issue, the underbump metallization layer has to provide an adequate diffusion barrier to prevent the solder material, frequently a mixture of lead (Pb) and tin (Sn), from attacking the chip's underlying metallization layers and thereby destroying or negatively affecting their functionality. Moreover, migration of solder material, such as lead, to other sensitive device areas, for instance into the dielectric, where a radioactive decay in lead may also significantly affect the device performance, has to be effectively suppressed by the underbump metallization. Regarding current conductivity, the underbump metallization, which serves as an interconnect between the solder bump and the underlying metallization layer of the chip, has to exhibit a thickness and a specific resistance that does not inappropriately increase the overall resistance of the metallization pad/solder bump system. In addition, the underbump metallization will serve as a current distribution layer during electroplating of the solder bump material. Electroplating is presently the preferred deposition technique, since physical vapor deposition of solder bump material, which is also used in the art, requires a complex mask technology in order to avoid any misalignments due to thermal expansion of the mask while it is contacted by the hot metal vapors. Moreover, it is extremely difficult to remove the metal mask after completion of the deposition process without damaging the solder pads, particularly when large wafers are processed or the pitch between adjacent solder pads decreases.
Although a mask is also used in the electroplating deposition method, this technique differs from the evaporation method in that the mask is created using photolithography to thereby avoid the above-identified problems caused by physical vapor deposition techniques. After the formation of the solder bumps, the underbump metallization has to be patterned to electrically insulate the individual solder bumps from each other.
The above-described process flow for forming the solder bumps including the complex sequence for forming the underbump metallization layer is significantly affected by the surface properties of the passivation layer resulting from the preceding manufacturing steps for forming and patterning the passivation layer and the aluminum and barrier layers. Consequently, any changes in these process steps may strongly affect the subsequent process flow for providing the solder bumps. On the other hand, the deposition and the patterning of the terminal metal stack, i.e., the barrier layer, such as tantalum, and the aluminum layer, may contribute to the overall production cost and may also represent a cause of increased defect rate and thus reduced production yield, in particular at a manufacturing stage, in which most of the complex process steps have already been completed. Thus, several attempts have been proposed to omit the terminal metal stack and to form the corresponding solder bumps on the basis of the last metal layer of the metallization layer stack in order to reduce process complexity. As is set forth above, however, significant process adaptations in the subsequent process for forming the solder bumps including the underbump metallization layer may be required, thereby possibly contributing to increased process complexity and reduced yield, which may offset the advantages obtained by omitting the terminal metal layer stack.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.